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st sitronix ST7558 65 x 102 dot matrix lcd controller/driver ver 2.3 1/56 2005/10/05 1. introduction the ST7558 is a driver & controller lsi for graphic dot-matrix liquid crystal display systems. it contains 102 segment and 65 common with 1 icom driver circuits. this chip is connected directly to a microprocessor, accepts 4-line serial interface (spi), i 2 c interface or 8-bit parallel interface, display data can stores in an on-chip display data ram of 66 x 102 bits. it performs display data ram read/write operation with no external operating clock to minimize power consumption. in addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a display system with the fewest components. 2. features driver output circuits 102 segment outputs / 65 common outputs on-chip display data ram - capacity: 66x102=6732 bits microprocessor interface - 8-bit parallel bi-directional interface with 6800-series or 8080-series - 4-line spi (serial peripheral interface) available (only write operation) - i 2 c (inter-integrated circuit) interface on-chip low power analog circuit - generation of lcd supply voltage (externally vout voltage supply is possible) - generation of intermediate lcd bias voltages - oscillator requires no external components (external clock also possible) - voltage converter (x2, x3, x4, x5) - voltage regulator (temperature gradient -0.05%/ c ) - voltage follower - on-chip electronic contrast control function (128 stepsx2) - liquid crystal driving voltage : v0 -vss = max 12 v (external power supply) external resb (reset) pin logic supply voltage range v dd -v ss - 1.8 to 3.3v temperature range: -30 to +85 degree ST7558 6800 , 8080 , 4-line (without i 2 c interface) ST7558i i 2 c interface
ST7558 ver 2.3 2/56 2005/10/05 3. pad arrangement (cog) chip size: 10,220 um 1000 um bump pitch: pad no 1 ~ 148 , 250 ~ 272 : 75.5 um (com/seg) pad no 149 ~ 248 : 75 um (i/o) pad no 148 ~ 149 : 114 um pad no 248 ~ 249 : 93.5 um pad no 249 ~ 250 : 95.9 um bump size: pad no 1 ~ 125 , 137 ~ 248 , 250 ~ 261 : 55(x) um ?? 60(y) um pad no 249 : 92(x) um ?? 60(y) um pad no 126 ~ 136 , 262 ~ 272 : 60(x)um ?? 55(y) um bump height: 17 um chip thickness: 635 um y x (0,0) 1 261 137 125 272 262 136 126 mark 55 60 55 60 bump size of top & bottom bump size of right & left 250 249 248 res 92 60 bump size of res unit: um 75 60 30 15 15 (4766,410) unit:um 30 6 6 6 6 75 60 30 15 15 (-4766,410) unit: um 30 75 60 10 30 15 15 30 (4763,-410) unit:um 75 60 10 30 15 15 30 (-4763,-410) unit:um metal area bump area
ST7558 ver 2.3 3/56 2005/10/05 pad center coordinates(normal,my=0) pad no. pin name x y 1 com[42] 4681.0 389.0 2 com[41] 4605.5 389.0 3 com[40] 4530.0 389.0 4 com[39] 4454.5 389.0 5 com[38] 4379.0 389.0 6 com[37] 4303.5 389.0 7 com[36] 4228.0 389.0 8 com[35] 4152.5 389.0 9 com[34] 4077.0 389.0 10 com[33] 4001.5 389.0 11 com[32] 3926.0 389.0 12 reserve 3850.5 389.0 13 seg[0] 3775.0 389.0 14 seg[1] 3699.5 389.0 15 seg[2] 3624.0 389.0 16 seg[3] 3548.5 389.0 17 seg[4] 3473.0 389.0 18 seg[5] 3397.5 389.0 19 seg[6] 3322.0 389.0 20 seg[7] 3246.5 389.0 21 seg[8] 3171.0 389.0 22 seg[9] 3095.5 389.0 23 seg[10] 3020.0 389.0 24 seg[11] 2944.5 389.0 25 seg[12] 2869.0 389.0 26 seg[13] 2793.5 389.0 27 seg[14] 2718.0 389.0 28 seg[15] 2642.5 389.0 29 seg[16] 2567.0 389.0 30 seg[17] 2491.5 389.0 31 seg[18] 2416.0 389.0 32 seg[19] 2340.5 389.0 33 seg[20] 2265.0 389.0 34 seg[21] 2189.5 389.0 35 seg[22] 2114.0 389.0 pad no. pin name x y 36 seg[23] 2038.5 389.0 37 seg[24] 1963.0 389.0 38 seg[25] 1887.5 389.0 39 seg[26] 1812.0 389.0 40 seg[27] 1736.5 389.0 41 seg[28] 1661.0 389.0 42 seg[29] 1585.5 389.0 43 seg[30] 1510.0 389.0 44 seg[31] 1434.5 389.0 45 seg[32] 1359.0 389.0 46 seg[33] 1283.5 389.0 47 seg[34] 1208.0 389.0 48 seg[35] 1132.5 389.0 49 seg[36] 1057.0 389.0 50 seg[37] 981.5 389.0 51 seg[38] 906.0 389.0 52 seg[39] 830.5 389.0 53 seg[40] 755.0 389.0 54 seg[41] 679.5 389.0 55 seg[42] 604.0 389.0 56 seg[43] 528.5 389.0 57 seg[44] 453.0 389.0 58 seg[45] 377.5 389.0 59 seg[46] 302.0 389.0 60 seg[47] 226.5 389.0 61 seg[48] 151.0 389.0 62 seg[49] 75.5 389.0 63 seg[50] 0.0 389.0 64 seg[51] -75.5 389.0 65 seg[52] -151.0 389.0 66 seg[53] -226.5 389.0 67 seg[54] -302.0 389.0 68 seg[55] -377.5 389.0 69 seg[56] -453.0 389.0 70 seg[57] -528.5 389.0
ST7558 ver 2.3 4/56 2005/10/05 pad no. pin name x y 71 seg[58] -604.0 389.0 72 seg[59] -679.5 389.0 73 seg[60] -755.0 389.0 74 seg[61] -830.5 389.0 75 seg[62] -906.0 389.0 76 seg[63] -981.5 389.0 77 seg[64] -1057.0 389.0 78 seg[65] -1132.5 389.0 79 seg[66] -1208.0 389.0 80 seg[67] -1283.5 389.0 81 seg[68] -1359.0 389.0 82 seg[69] -1434.5 389.0 83 seg[70] -1510.0 389.0 84 seg[71] -1585.5 389.0 85 seg[72] -1661.0 389.0 86 seg[73] -1736.5 389.0 87 seg[74] -1812.0 389.0 88 seg[75] -1887.5 389.0 89 seg[76] -1963.0 389.0 90 seg[77] -2038.5 389.0 91 seg[78] -2114.0 389.0 92 seg[79] -2189.5 389.0 93 seg[80] -2265.0 389.0 94 seg[81] -2340.5 389.0 95 seg[82] -2416.0 389.0 96 seg[83] -2491.5 389.0 97 seg[84] -2567.0 389.0 98 seg[85] -2642.5 389.0 99 seg[86] -2718.0 389.0 100 seg[87] -2793.5 389.0 101 seg[88] -2869.0 389.0 102 seg[89] -2944.5 389.0 103 seg[90] -3020.0 389.0 104 seg[91] -3095.5 389.0 105 seg[92] -3171.0 389.0 106 seg[93] -3246.5 389.0 pad no. pin name x y 107 seg[94] -3322.0 389.0 108 seg[95] -3397.5 389.0 109 seg[96] -3473.0 389.0 110 seg[97] -3548.5 389.0 111 seg[98] -3624.0 389.0 112 seg[99] -3699.5 389.0 113 seg[100] -3775.0 389.0 114 seg[101] -3850.5 389.0 115 coms1 -3926.0 389.0 116 com[0] -4001.5 389.0 117 com[1] -4077.0 389.0 118 com[2] -4152.5 389.0 119 com[3] -4228.0 389.0 120 com[4] -4303.5 389.0 121 com[5] -4379.0 389.0 122 com[6] -4454.5 389.0 123 com[7] -4530.0 389.0 124 com[8] -4605.5 389.0 125 com[9] -4681.0 389.0 126 com[10] -4998.5 381.5 127 com[11] -4998.5 306.0 128 com[12] -4998.5 230.5 129 com[13] -4998.5 155.0 130 com[14] -4998.5 79.5 131 com[15] -4998.5 4.0 132 com[16] -4998.5 -71.5 133 com[17] -4998.5 -147.0 134 com[18] -4998.5 -222.5 135 com[19] -4998.5 -298.0 136 com[20] -4998.5 -373.5 137 com[21] -4694.5 -389.0 138 com[22] -4619.0 -389.0 139 com[23] -4543.5 -389.0 140 com[24] -4468.0 -389.0 141 com[25] -4392.5 -389.0 142 com[26] -4317.0 -389.0
ST7558 ver 2.3 5/56 2005/10/05 pad no. pin name x y 143 com[27] -4241.5 -389.0 144 com[28] -4166.0 -389.0 145 com[29] -4090.5 -389.0 146 com[30] -4015.0 -389.0 147 com[31] -3939.5 -389.0 148 reserve -3864.0 -389.0 149 t9 -3750.0 -389.0 150 vdd -3675.0 -389.0 151 vdd -3600.0 -389.0 152 vdd -3525.0 -389.0 153 vdd -3450.0 -389.0 154 vdd -3375.0 -389.0 155 vdd -3300.0 -389.0 156 vdd2 -3225.0 -389.0 157 vdd2 -3150.0 -389.0 158 vdd2 -3075.0 -389.0 159 vdd2 -3000.0 -389.0 160 vdd2 -2925.0 -389.0 161 vdd2 -2850.0 -389.0 162 vdd2 -2775.0 -389.0 163 vdd2 -2700.0 -389.0 164 vdd2 -2625.0 -389.0 165 vdd2 -2550.0 -389.0 166 vdd2 -2475.0 -389.0 167 vdd2 -2400.0 -389.0 168 d7 -2325.0 -389.0 169 d7 -2250.0 -389.0 170 d6 -2175.0 -389.0 171 d6 -2100.0 -389.0 172 d5 -2025.0 -389.0 173 d5 -1950.0 -389.0 174 d4 -1875.0 -389.0 175 d4 -1800.0 -389.0 176 d3 -1725.0 -389.0 177 d3 -1650.0 -389.0 178 d2 -1575.0 -389.0 pad no. pin name x y 179 d2 -1500.0 -389.0 180 d1 -1425.0 -389.0 181 d1 -1350.0 -389.0 182 d0 -1275.0 -389.0 183 d0 -1200.0 -389.0 184 vdd -1125.0 -389.0 185 t0 -1050.0 -389.0 186 t1 -975.0 -389.0 187 t2 -900.0 -389.0 188 t3 -825.0 -389.0 189 t4 -750.0 -389.0 190 t5 -675.0 -389.0 191 t6 -600.0 -389.0 192 t7 -525.0 -389.0 193 t8 -450.0 -389.0 194 vrs -375.0 -389.0 195 erd -300.0 -389.0 196 erd -225.0 -389.0 197 rwr -150.0 -389.0 198 rwr -75.0 -389.0 199 a0 0.0 -389.0 200 a0 75.0 -389.0 201 cs 150.0 -389.0 202 cs 225.0 -389.0 203 ims 300.0 -389.0 204 vdd 375.0 -389.0 205 ps 450.0 -389.0 206 t11 525.0 -389.0 207 t10 600.0 -389.0 208 vdd 675.0 -389.0 209 osc 750.0 -389.0 210 osc 825.0 -389.0 211 v0 900.0 -389.0 212 v0 975.0 -389.0 213 v0 1050.0 -389.0 214 v0 1125.0 -389.0
ST7558 ver 2.3 6/56 2005/10/05 pad no. pin name x y 215 v1 1200.0 -389.0 216 v2 1275.0 -389.0 217 v3 1350.0 -389.0 218 v4 1425.0 -389.0 219 vss2 1500.0 -389.0 220 vss2 1575.0 -389.0 221 vss2 1650.0 -389.0 222 vss2 1725.0 -389.0 223 vss2 1800.0 -389.0 224 vss2 1875.0 -389.0 225 vss2 1950.0 -389.0 226 vss2 2025.0 -389.0 227 vss2 2100.0 -389.0 228 vss2 2175.0 -389.0 229 vss2 2250.0 -389.0 230 vss2 2325.0 -389.0 231 vss 2400.0 -389.0 232 vss 2475.0 -389.0 233 vss 2550.0 -389.0 234 vss 2625.0 -389.0 235 vss 2700.0 -389.0 236 vss 2775.0 -389.0 237 vlcdin 2850.0 -389.0 238 vlcdin 2925.0 -389.0 239 vlcdin 3000.0 -389.0 240 vlcdin 3075.0 -389.0 241 vlcdin 3150.0 -389.0 242 vlcdin 3225.0 -389.0 243 vlcdout 3300.0 -389.0 pad no. pin name x y 244 vlcdout 3375.0 -389.0 245 vlcdout 3450.0 -389.0 246 vlcdout 3525.0 -389.0 247 vlcdout 3600.0 -389.0 248 vlcdout 3675.0 -389.0 249 res 3768.5 -389.0 250 coms2 3864.5 -389.0 251 com[64] 3940.0 -389.0 252 com[63] 4015.5 -389.0 253 com[62] 4091.0 -389.0 254 com[61] 4166.5 -389.0 255 com[60] 4242.0 -389.0 256 com[59] 4317.5 -389.0 257 com[58] 4393.0 -389.0 258 com[57] 4468.5 -389.0 259 com[56] 4544.0 -389.0 260 com[55] 4619.5 -389.0 261 com[54] 4695.0 -389.0 262 com[53] 4998.5 -373.5 263 com[52] 4998.5 -298.0 264 com[51] 4998.5 -222.5 265 com[50] 4998.5 -147.0 266 com[49] 4998.5 -71.5 267 com[48] 4998.5 4.0 268 com[47] 4998.5 79.5 269 com[46] 4998.5 155.0 270 com[45] 4998.5 230.5 271 com[44] 4998.5 306.0 272 com[43] 4998.5 381.5
ST7558 ver 2.3 7/56 2005/10/05 pad center coordina tes(reverse,my=1) pad no. pin name x y 1 com[22] 4681.0 389.0 2 com[23] 4605.5 389.0 3 com[24] 4530.0 389.0 4 com[25] 4454.5 389.0 5 com[26] 4379.0 389.0 6 com[27] 4303.5 389.0 7 com[28] 4228.0 389.0 8 com[29] 4152.5 389.0 9 com[30] 4077.0 389.0 10 com[31] 4001.5 389.0 11 reserve 3926.0 389.0 12 reserve 3850.5 389.0 13 seg[0] 3775.0 389.0 14 seg[1] 3699.5 389.0 15 seg[2] 3624.0 389.0 16 seg[3] 3548.5 389.0 17 seg[4] 3473.0 389.0 18 seg[5] 3397.5 389.0 19 seg[6] 3322.0 389.0 20 seg[7] 3246.5 389.0 21 seg[8] 3171.0 389.0 22 seg[9] 3095.5 389.0 23 seg[10] 3020.0 389.0 24 seg[11] 2944.5 389.0 25 seg[12] 2869.0 389.0 26 seg[13] 2793.5 389.0 27 seg[14] 2718.0 389.0 28 seg[15] 2642.5 389.0 29 seg[16] 2567.0 389.0 30 seg[17] 2491.5 389.0 31 seg[18] 2416.0 389.0 32 seg[19] 2340.5 389.0 33 seg[20] 2265.0 389.0 34 seg[21] 2189.5 389.0 35 seg[22] 2114.0 389.0 pad no. pin name x y 36 seg[23] 2038.5 389.0 37 seg[24] 1963.0 389.0 38 seg[25] 1887.5 389.0 39 seg[26] 1812.0 389.0 40 seg[27] 1736.5 389.0 41 seg[28] 1661.0 389.0 42 seg[29] 1585.5 389.0 43 seg[30] 1510.0 389.0 44 seg[31] 1434.5 389.0 45 seg[32] 1359.0 389.0 46 seg[33] 1283.5 389.0 47 seg[34] 1208.0 389.0 48 seg[35] 1132.5 389.0 49 seg[36] 1057.0 389.0 50 seg[37] 981.5 389.0 51 seg[38] 906.0 389.0 52 seg[39] 830.5 389.0 53 seg[40] 755.0 389.0 54 seg[41] 679.5 389.0 55 seg[42] 604.0 389.0 56 seg[43] 528.5 389.0 57 seg[44] 453.0 389.0 58 seg[45] 377.5 389.0 59 seg[46] 302.0 389.0 60 seg[47] 226.5 389.0 61 seg[48] 151.0 389.0 62 seg[49] 75.5 389.0 63 seg[50] 0.0 389.0 64 seg[51] -75.5 389.0 65 seg[52] -151.0 389.0 66 seg[53] -226.5 389.0 67 seg[54] -302.0 389.0 68 seg[55] -377.5 389.0 69 seg[56] -453.0 389.0 70 seg[57] -528.5 389.0
ST7558 ver 2.3 8/56 2005/10/05 pad no. pin name x y 71 seg[58] -604.0 389.0 72 seg[59] -679.5 389.0 73 seg[60] -755.0 389.0 74 seg[61] -830.5 389.0 75 seg[62] -906.0 389.0 76 seg[63] -981.5 389.0 77 seg[64] -1057.0 389.0 78 seg[65] -1132.5 389.0 79 seg[66] -1208.0 389.0 80 seg[67] -1283.5 389.0 81 seg[68] -1359.0 389.0 82 seg[69] -1434.5 389.0 83 seg[70] -1510.0 389.0 84 seg[71] -1585.5 389.0 85 seg[72] -1661.0 389.0 86 seg[73] -1736.5 389.0 87 seg[74] -1812.0 389.0 88 seg[75] -1887.5 389.0 89 seg[76] -1963.0 389.0 90 seg[77] -2038.5 389.0 91 seg[78] -2114.0 389.0 92 seg[79] -2189.5 389.0 93 seg[80] -2265.0 389.0 94 seg[81] -2340.5 389.0 95 seg[82] -2416.0 389.0 96 seg[83] -2491.5 389.0 97 seg[84] -2567.0 389.0 98 seg[85] -2642.5 389.0 99 seg[86] -2718.0 389.0 100 seg[87] -2793.5 389.0 101 seg[88] -2869.0 389.0 102 seg[89] -2944.5 389.0 103 seg[90] -3020.0 389.0 104 seg[91] -3095.5 389.0 105 seg[92] -3171.0 389.0 106 seg[93] -3246.5 389.0 pad no. pin name x y 107 seg[94] -3322.0 389.0 108 seg[95] -3397.5 389.0 109 seg[96] -3473.0 389.0 110 seg[97] -3548.5 389.0 111 seg[98] -3624.0 389.0 112 seg[99] -3699.5 389.0 113 seg[100] -3775.0 389.0 114 seg[101] -3850.5 389.0 115 coms1 -3926.0 389.0 116 com[64] -4001.5 389.0 117 com[63] -4077.0 389.0 118 com[62] -4152.5 389.0 119 com[61] -4228.0 389.0 120 com[60] -4303.5 389.0 121 com[59] -4379.0 389.0 122 com[58] -4454.5 389.0 123 com[57] -4530.0 389.0 124 com[56] -4605.5 389.0 125 com[55] -4681.0 389.0 126 com[54] -4998.5 381.5 127 com[53] -4998.5 306.0 128 com[52] -4998.5 230.5 129 com[51] -4998.5 155.0 130 com[50] -4998.5 79.5 131 com[49] -4998.5 4.0 132 com[48] -4998.5 -71.5 133 com[47] -4998.5 -147.0 134 com[46] -4998.5 -222.5 135 com[45] -4998.5 -298.0 136 com[44] -4998.5 -373.5 137 com[43] -4694.5 -389.0 138 com[42] -4619.0 -389.0 139 com[41] -4543.5 -389.0 140 com[40] -4468.0 -389.0 141 com[39] -4392.5 -389.0 142 com[38] -4317.0 -389.0
ST7558 ver 2.3 9/56 2005/10/05 pad no. pin name x y 143 com[37] -4241.5 -389.0 144 com[36] -4166.0 -389.0 145 com[35] -4090.5 -389.0 146 com[34] -4015.0 -389.0 147 com[33] -3939.5 -389.0 148 com[32] -3864.0 -389.0 149 t9 -3750.0 -389.0 150 vdd -3675.0 -389.0 151 vdd -3600.0 -389.0 152 vdd -3525.0 -389.0 153 vdd -3450.0 -389.0 154 vdd -3375.0 -389.0 155 vdd -3300.0 -389.0 156 vdd2 -3225.0 -389.0 157 vdd2 -3150.0 -389.0 158 vdd2 -3075.0 -389.0 159 vdd2 -3000.0 -389.0 160 vdd2 -2925.0 -389.0 161 vdd2 -2850.0 -389.0 162 vdd2 -2775.0 -389.0 163 vdd2 -2700.0 -389.0 164 vdd2 -2625.0 -389.0 165 vdd2 -2550.0 -389.0 166 vdd2 -2475.0 -389.0 167 vdd2 -2400.0 -389.0 168 d7 -2325.0 -389.0 169 d7 -2250.0 -389.0 170 d6 -2175.0 -389.0 171 d6 -2100.0 -389.0 172 d5 -2025.0 -389.0 173 d5 -1950.0 -389.0 174 d4 -1875.0 -389.0 175 d4 -1800.0 -389.0 176 d3 -1725.0 -389.0 177 d3 -1650.0 -389.0 178 d2 -1575.0 -389.0 pad no. pin name x y 179 d2 -1500.0 -389.0 180 d1 -1425.0 -389.0 181 d1 -1350.0 -389.0 182 d0 -1275.0 -389.0 183 d0 -1200.0 -389.0 184 vdd -1125.0 -389.0 185 t0 -1050.0 -389.0 186 t1 -975.0 -389.0 187 t2 -900.0 -389.0 188 t3 -825.0 -389.0 189 t4 -750.0 -389.0 190 t5 -675.0 -389.0 191 t6 -600.0 -389.0 192 t7 -525.0 -389.0 193 t8 -450.0 -389.0 194 vrs -375.0 -389.0 195 erd -300.0 -389.0 196 erd -225.0 -389.0 197 rwr -150.0 -389.0 198 rwr -75.0 -389.0 199 a0 0.0 -389.0 200 a0 75.0 -389.0 201 cs 150.0 -389.0 202 cs 225.0 -389.0 203 ims 300.0 -389.0 204 vdd 375.0 -389.0 205 ps 450.0 -389.0 206 t11 525.0 -389.0 207 t10 600.0 -389.0 208 vdd 675.0 -389.0 209 osc 750.0 -389.0 210 osc 825.0 -389.0 211 v0 900.0 -389.0 212 v0 975.0 -389.0 213 v0 1050.0 -389.0 214 v0 1125.0 -389.0
ST7558 ver 2.3 10/56 2005/10/05 pad no. pin name x y 215 v1 1200.0 -389.0 216 v2 1275.0 -389.0 217 v3 1350.0 -389.0 218 v4 1425.0 -389.0 219 vss2 1500.0 -389.0 220 vss2 1575.0 -389.0 221 vss2 1650.0 -389.0 222 vss2 1725.0 -389.0 223 vss2 1800.0 -389.0 224 vss2 1875.0 -389.0 225 vss2 1950.0 -389.0 226 vss2 2025.0 -389.0 227 vss2 2100.0 -389.0 228 vss2 2175.0 -389.0 229 vss2 2250.0 -389.0 230 vss2 2325.0 -389.0 231 vss 2400.0 -389.0 232 vss 2475.0 -389.0 233 vss 2550.0 -389.0 234 vss 2625.0 -389.0 235 vss 2700.0 -389.0 236 vss 2775.0 -389.0 237 vlcdin 2850.0 -389.0 238 vlcdin 2925.0 -389.0 239 vlcdin 3000.0 -389.0 240 vlcdin 3075.0 -389.0 241 vlcdin 3150.0 -389.0 242 vlcdin 3225.0 -389.0 243 vlcdout 3300.0 -389.0 pad no. pin name x y 244 vlcdout 3375.0 -389.0 245 vlcdout 3450.0 -389.0 246 vlcdout 3525.0 -389.0 247 vlcdout 3600.0 -389.0 248 vlcdout 3675.0 -389.0 249 res 3768.5 -389.0 250 coms2 3864.5 -389.0 251 com[0] 3940.0 -389.0 252 com[1] 4015.5 -389.0 253 com[2] 4091.0 -389.0 254 com[3] 4166.5 -389.0 255 com[4] 4242.0 -389.0 256 com[5] 4317.5 -389.0 257 com[6] 4393.0 -389.0 258 com[7] 4468.5 -389.0 259 com[8] 4544.0 -389.0 260 com[9] 4619.5 -389.0 261 com[10] 4695.0 -389.0 262 com[11] 4998.5 -373.5 263 com[12] 4998.5 -298.0 264 com[13] 4998.5 -222.5 265 com[14] 4998.5 -147.0 266 com[15] 4998.5 -71.5 267 com[16] 4998.5 4.0 268 com[17] 4998.5 79.5 269 com[18] 4998.5 155.0 270 com[19] 4998.5 230.5 271 com[20] 4998.5 306.0 272 com[21] 4998.5 381.5
ST7558 ver 2.3 11/56 2005/10/05 4. block diagram /res /cs a0 rd(e) wr(r/w) db7(scl) db6(si) db5 db4 db3 db2 db1 db0 fig.1 block diagram
ST7558 ver 2.3 12/56 2005/10/05 5. pinning descriptions pin name i/o description no. of pins lcd driver outputs seg0 to seg101 o lcd segment driver outputs this display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m (internal) normal display reverse display h h vlcd v 2 h l v ss v 3 l h v 2 vlcd l l v 3 v ss power save mode v ss v ss 102 com0 to com64 o lcd column driver outputs this internal scanning data and m signal control the output voltage of common driver. common driver output voltage display data m(internal) normal display reverse display h h v ss h l vlcd l h v 1 l l v 4 power save mode v ss 65 coms o common output for the icons the output signals of two pins are same. when not used, this pin should be left open. 2 microprocessor interface p/s i microprocessor interface select input pin p/s= " h ?: parallel data input. p/s= " l ?: serial data input. when p/s=" l ",d0 to d5 are fixed to " h ". rd (e) and wr(r/w) are fixed to " h ". 1 ims i input mode select p/s ims state " h " " h " 6800-series parallel mpu interface " h " " l " 8080-series parallel mpu interface " l " " h " 4 pin-spi mpu interface " l " " l " i 2 c interface 1 csb i chip select input pins data/instruction i/o is enabled only when csb is " l ". when chip select is non-active, db0 to db7 is high impedance. when csb pin in two line interface, this pin should fix to ? h? 2 resb i reset input pin when reset is " l ", initialization is executed. 1 a0 i it determines whether the data bits are data or a command. a0=" h ?: indicates that d0 to d7 are display data. a0=" l ?: indicates that d0 to d7 are control data. a0 pin in i 2 c interface, this pin should fix to ? h? 2
ST7558 ver 2.3 13/56 2005/10/05 /wr(r/w) i read/write execution control pin ims mpu type /wr(r/w) description h 6800-series r/w read/write control input pin r/w=" h ?: read r/w=" l?: write l 8080-series /wr write enable clock input pin the data on d0 to d7 are latched at the rising edge of the /wr signal when in the serial interface must fixed to " h ". 2 /rd (e) i read/write execution control pin ims mpu type /rd (e) description h 6800-series e read/write control input pin r/w=" h ?: when e is " h ", d0 to d7 are in an output status. r/w=" l ?: the data on d0 to d7 are latched at the falling edge of the e signal. l 8080-series /rd read enable clock input pin when /rd is " l ", d0 to d7 are in an output status. when in the serial interface must fixed to " h ". 2 when the parallel interface selected (p/s=" h " ): 8-bit interface 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. when chip select is not active, d0 to d7 is high impedance. d5 to d0 d6 (si) d7 (scl) when the serial interface selected (p/s=" l " & ims=?h?):4-line d7: serial input clock (scl) d6: serial input data (si) d5, d4, d3, d2, d1, d0: must fix to ?h?.. when chip select is not active, d0 to d7 is high impedance. d0 to d1 (sa) d2 to d3 (sda_out) d4 to d6 (sda_in) d7 (scl) i/o when the serial interface selected (p/s=" l " & ims=?l?): i 2 c d7: serial clock input (scl) d6 , d5 , d4: serial input data (sda_in) d3, d2: (sda_out) serial data acknowledge for the i 2 c interface. by connecting sda_out to sda_in externally, the sda line becomes fully i 2 c interface compatible. having the acknowledge output separated from the serial data line is advantageous in chip on glass (cog) applications. in cog application where the track resistance from the sda_out pad to the system sda line can be significant, a potential divider is generated by the bus pull-up resistor and the ito track resistance. it is possible the during the acknowledge cycle the ST7558 will not be able to create a valid logic 0 level. by splitting the sda_in input from the sda_out output the device could be used in a mode that ignores the acknowledge bit. in cog applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the sda_out pad to the system sda line to guarantee a valid low level. d6, d5, ?.d2 must be connected together (sda) d1, d0: is slave address (sa) bit1, 0, must fix to ?h? or ?l? chip select input pins ?csb? not used must fix to ?h? 16
ST7558 ver 2.3 14/56 2005/10/05 lcd driver supply osc i when the on-chip oscillator is used, this input must be connected to vdd. an external clock signal, if used, is connected to this input. if the oscillator and external clock are both inhibited by connecting the osc pin to vss the display is not clocked and may be left in a dc state. to avoid this, the chip should always be put into power down mode before stopping the clock. 2 power supply pins v ss1 power supply digital ground. the 2 supply rails v ss1 and v ss2 must be connected together. 6 v ss2 power supply analog ground. the 2 supply rails v ss1 and v ss2 must be connected together. 12 vdd power supply digital supply voltage. the 2 supply rails vdd and v dd2 could be connected together. if digital option pin is high, must be this level 9 v dd2 power supply analog supply voltage. the 2 supply rails vdd and v dd2 could be connected together. 12 v lcdout power supply if the internal voltage generator is used, the v lcdin & v lcdout must be connected together and series one capacitor to vss2. if an external supply is used this pin must be left open. 6 v lcdin power supply if the internal voltage generator is used, the v lcdin & v lcdout must be connected together. an external supply voltage can be supplied using the v lcdin pad. this pad is for external multiple voltage input. in this case, vlcdout has to be left open, 6 v0,v1, v2, v3, v4 power supply this is a multi-level power supply for the liquid crystal. v lcdin v0 v1 v2 v3 v4 vss 8 vrs power supply monitor voltage regulator level, must be left open. 1 test pin te s t 0 ~ te s t 11 t to test used. test0~test8 must floating test9 could be connected out for monitor the vlcd(v0) voltage test10 must connect to vss test11 must connect to vdd 11 reserve pin all reserve pin must floating ST7558 i/o pin ito resister limitation pin name ito resister ps,ims,osc no limitation t1~t8, vrs, v1 , v2 , v3 , v4 floating vdd, vdd2, vss1, vss2 , vlcdin , vlcdout <100 ? t9,v0 <500 ? a0,/wr,/rd,csb, d0 ?d7(68/80, 4l-spi interface) <1k ? resb <10k ? in iic interface: sda , scl ito resister recommend to less than 100 ohm
ST7558 ver 2.3 15/56 2005/10/05 6. functions description microprocessor interface chip select input there is csb pin for chip selection. the ST7558 can interface with an mpu when csb is "l". when csb is ?h?, these pins are set to any other combination, a0, /rd(e), and /wr(r/w) inputs are disabled and d0 to d7 are to be high impedance. and, in case of serial interface, the internal shift register and the counter are reset. parallel / serial interface ST7558 has four types of interface with an mpu, which are two serial and two parallel interfaces. this parallel or serial interface is determined by p/s pin as shown in table 1. table 1. parallel/serial interface mode type p/s ims csb interface mode h 6800-series mpu interface parallel h l csb 8080-series mpu interface h csb 4-pin spi interface serial l l --- i 2 c interface parallel interface (p/s = "h") the 8-bit bi-directional data bus is used in parallel interface and the type of mpu is selected by ims as shown in table 2. the type of data transfer is determined by signals at a0, /rd (e) and /wr(r/w) as shown in t ab le 3. table 2. microprocessor selection for parallel interface ims csb a0 /rd (e) /wr (r/w) db0 to db7 mpu bus h csb a0 e r/w db0 to db7 6800-series l csb a0 /rd /wr db0 to db7 8080-series table 3. parallel data transfer common 6800-series 8080-series rs e (/rd) r/w (/wr) /rd (e) /wr (r/w) description h h h l h display data read out h h l h l display data write l h h l h register status read l h l h l writes to internal register (instruction) note: when /rd (e) pin is always pulled high for 6800-series interface, it can be used csb for enable signal. in this case, interface data is latched at the rising edge of csb and the type of data transfer is determined by signals at a0, /wr(r/w) as in case of 6800-series mode. serial interface (p/s = " l ") serial mode p/s ims csb a0 description 4-line spi interface l h csb used write only i 2 c interface l l not used fix to ?h? not used fix to ?h? write only ims=? l ?, p/s=? h ?: 4-line spi interface when the ST7558 is active (csb=?l?), serial data (d6) and serial clock (d7) inputs are enabled. and not active, the internal 8-bit shift register and the 3-bit counter are reset. the display data/command indication may be controlled either via software or the register select (a0) pin, based on the setting of p/s. when the a0 pin is used (ims = ?h?), data is display data when a0 is high, and command data when a0 is low. when a0 is not used (ims = ?l?), the lcd driver will receive command from mcu by default. if messages on the data pin are data rather than command, mcu should send data direction command to control the data direction and then one more command to define the number of data bytes will be write. after these two continuous commands are sending, the following messages will be data rather than command. serial data can be read on the rising edge of serial clock going into d7 and processed as 8-bit parallel data on the eighth serial clock. and the ddram column address poin ter will be increased by one automatically. the next bytes after the display data string are handled as command data.
ST7558 ver 2.3 16/56 2005/10/05 db7 db6 db5 db4 db3 db2 db1 db0 db7 db6 csb sda scl a0 fig. 2 4-line spi timing ims=? l ?, p/s=? l ?: i 2 c interface it could not read data or instruction from ST7558 (except acknowledge signal). scl: serial clock input sda_in: serial data input sda_out: acknowledge response output slave address could set from ?0111100? to ?0111111?. the i 2 c interface send ram data and executes the commands sent via the i 2 c interface. it could send data in to the ram. the i 2 c interface is two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. bit transfer is illustra ted in fig.3. start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high tr ansition of the data line while the clock is high is defined as the stop condition (p). the start and st op conditions are illustrated in fig.4. system configuration the system configuration is illustrated in fig.5. transmitter: the device, which sends the data to the bus master: the device, which initiates a transfer, generates clock signals and terminates a transfer slave: the device addressed by a master multi-master: more than one master can attempt to control the bus at the same time without corrupting the message arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted synchronization: procedure to synchronize the clock signals of two or more devices. acknowledge acknowledge signal (ack) is not bf signal in parallel interface. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. a master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c interface is illustrated in fig.6.
ST7558 ver 2.3 17/56 2005/10/05 sda scl data line stable; data valid change of data allowed fig .3 bit transfer sda scl sp start condition stop condition fig .4 definition of st art and stop conditions master transmitter/ receiver slave receiver (1) 0111100 slave receiver (2) 0111101 slave receiver (3) 0111110 slave receiver (4) 0111111 sda scl fig .5 system configuration
ST7558 ver 2.3 18/56 2005/10/05 i 2 c interface protocol the ST7558 supports command, data write addressed slaves on the bus. before any data is transmitted on the i 2 c interface, the device, which should respond, is addressed first. four 7-bit slave addresses (01111 00 to 01111 11 ) are reserved for the ST7558. the r/w is assigned to 0 for write only. the i 2 c interface protocol is illustrated in fig.7. the sequence is initiated with a start condition (s) from the i 2 c interface master, which is followed by the slave address. all slaves with the corresponding address acknowledge in parallel, all the others will ignore the i 2 c interface transfer. after acknowledgement, one or more command words follow which define the status of the addressed slaves. a command word consists of a control byte, which defines co and rs, plus a data byte. the last control byte is tagged with a cleared most significant bit (i.e. the continuation bit co). after a control byte with a cleared co bit, only data bytes will follow. the state of the rs bit defines whether the data byte is interpreted as a command or as ram data. all addressed slaves on the bus also acknowledge the control and data bytes. after the last control byte, depending on the rs bit setting; either a series of display data bytes or command data bytes may follow. if the rs bit is set to logic 1, these display bytes are stored in the display ram at the address specified by the data pointer. the data pointer is automatically updated and the data is directed to the intended st558 device. if the rs bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. only the addressed slave makes the acknowledgement after each byte. at the end of the transmission the i 2 c interface-bus master issues a stop condition (p).if the r/w bit is set to logic 1 the chip will output data immediately after the slave address if the rs bit, which was sent during the last write access, is set to logic 0. if no acknowledge is generated by the master after a byte, the driver stops transferring data to the master. 1 2 89 s data output by transmitter data output by receiver scl from master start condition not acknowledge acknowledge clock pulse for acknowledge ment fig .6 acknowledgement on the i 2 c interface
ST7558 ver 2.3 19/56 2005/10/05 busy flag the busy flag indicates whether the ST7558 is operating or not. when d7 is "h" in read status operation, this device is in busy status and will accept only read status instruction. if th e cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the mpu performance. data transfer the ST7558 uses bus holder and internal data bus for data transfer with the mpu. when writing data from the mpu to on-chip ram, data is automatically transferred from the bus holder to the ram as shown in figure 8. and when reading data from on-chip ram to the mpu, the data for the initial read cycle is stored in the bus holder (dummy read) and the mpu reads this stored data from bus holder for the next data read cycle as shown in figure 9. this means that a dummy read cycle must be inserted between each pair of address sets w hen a sequence of address sets is executed. therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. n d(n) d(n+1) d(n+2) d(n+3) n d(n) d(n+1) d(n+2) d(n+3) nn+1n+2 n+3 mpu signal a0 /wr d0 to d7 internal signals /wr bus holder column address fig.8 write timing s 01111 1 r s 0 a control byte a data byte co 0 r s a control byte a data byte a p co slave address acknowledgement from ST7558 acknowledgement from ST7558 acknowledgement from ST7558 acknowledgement from ST7558 acknowledgement from ST7558 2n>=0bytes command word n>=0bytes msb.......................lsb 1 byte r/w write mode 01111 r / w slave address co r s 000000 control byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data byte 1 0 1 0 fig .7 i 2 c interface protocol 0 last control byte to be sent. only a stream of data bytes is allowed to follow. this stream may only be terminated by a stop condition. co
ST7558 ver 2.3 20/56 2005/10/05 display data ram (ddram) the ST7558 contains a 65x102 bit static ram that stores the display data. the display data ram store the dot data for the lcd. it has a 65(8 pagex8 +1) x102, and extra icom. there is a direct correspondence between x-address and column output number. it is 65-row by 102-column addressable array. each pixel can be selected when the page and column addresses are specified. the 65 rows are divided into 8 pages of 8 lines and 1 page of 1 line. data is read from or written to the 8 lines of each page directly through d0 to d7. the display data of d0 to d7 from the microprocessor correspond to the lcd common lines. the microprocessor can read from and wr ite to ram through the i/o buffer. since the lcd controller operates independently, data can be written into ram at the same time as data is being displayed without causing the lcd flicker. n dummy d(n) d(n+1) mpu signal a0 /w r d0 to d7 internal signals /w r column address /rd n d(n) d(n+1) d(n+2) d(n) d(n+1) d(n+2) n /rd bus holder fig.9 read timing
ST7558 ver 2.3 21/56 2005/10/05 page address circuit this circuit is for providing a page address to display data ram shown in figure 10. it incorporates 4-bit page address register changed by only the ?set page? instructio n. page address 9 is a special ram area for the icons and display data d0 is only valid. column address circuit column address circuit has an 8-bit preset counter that prov ides column address to the display data ram as shown in figure10. the display data ram column address is specified by the column address set command. the specified column address is incremented (+1) with each display data read/write co mmand. this allows the mpu display data to be accessed continuously. register mx and my selection instruction makes it possible to invert the relationship between the column address and the segment outputs. it is necessary to rewrite the display data on built-in ram after issuing mx select instruction. seg output seg output mx seg0 seg101 ?0? seg0 ? segment address ? seg101 ?1? seg101 ? segment address ? seg0 com output com output my com0 com64 ?0? com0 ? common address ? com64 ?1? com64 ? common address ? com0 addressing data is downloaded in bytes into the ram matrix of ST7558 as indicated in figs.10, 11,12. the display ram has a matrix of 65 by 102 bits. the address pointer addresses the columns. the address ranges are: x 0 to 101 (1100101), y 0 to 8 (1000). addresses outside these ranges are not allowed. in vertical addressing mode (v=1) the y address increments after each byte (see fig.11). after the last y address (y = 8) y wraps around to 0 and x increments to address the next column. in horizontal addressing mode (v=0) the x address increments after each byte (see fig.12). after the last x address (x = 101) x wraps around to 0 and y increments to address the next row. after the very last address (x = 101, y = 8) the address pointers wrap around to address (x = 0, y =0) data structure y-address lsb msb 0 101 x-address 1 bit d0 d7 0 1 2 3 4 5 6 7 8 d0 page 8 d7 9 1 bit d0 page 9 d7 1 bit icom fig.10 ram format, addressing
ST7558 ver 2.3 22/56 2005/10/05 0 1 2 3 4 5 101 0 x-address 0 y-address 6 7 8 1 2 3 4 5 6 7 8 17 917 18 19 20 21 22 23 24 25 26 9 10 11 12 13 14 15 16 fig.11 sequence of writing data bytes into ram with vertical addressing (v=1) 0 12 102 101 0 x-address y-address 103104 204205206 306307308 408409410 510511512 612613614 714715716 816817818 0 1 2 3 4 5 6 7 8 917 fig.12 sequence of writing data bytes into ram with horizontal addressing (v=0)
ST7558 ver 2.3 23/56 2005/10/05 page address d3 d2 d1 d0 data line address com output d0 00h com0 d1 01h com1 d2 02h com2 d3 03h com3 d4 04h com4 d5 05h com5 d6 06h com6 0 0 0 0 d7 page 0 07h com7 d0 08h com8 d1 09h com9 d2 0ah com10 d3 0bh com11 d4 0ch com12 d5 0dh com13 d6 0eh com14 0 0 0 1 d7 page 1 0fh com15 d0 10h com16 d1 11h com17 d2 12h com18 d3 13h com19 d4 14h com20 d5 15h com21 d6 16h com22 0 0 1 0 d7 page 2 17h com23 d0 18h com24 d1 19h com25 d2 1ah com26 d3 1bh com27 d4 1ch com28 d5 1dh com29 d6 1eh com30 0 0 1 1 d7 page 3 1fh com31 d0 20h com32 d1 21h com33 d2 22h com34 d3 23h com35 d4 24h com36 d5 25h com37 d6 26h com38 0 1 0 0 d7 page 4 27h com39 d0 28h com40 d1 29h com41 d2 2ah com42 d3 2bh com43 d4 2ch com44 d5 2dh com45 d6 2eh com46 0 1 0 1 d7 page 5 2fh com47 d0 30h com48 d1 31h com49 d2 32h com50 d3 33h com51 d4 34h com52 d5 35h com53 d6 36h com54 0 1 1 0 d7 page 6 37h com55 d0 38h com56 d1 39h com57 d2 3ah com58 d3 3bh com59 d4 3ch com60 d5 3dh com61 d6 3eh com62 0 1 1 1 d7 page 7 3fh com63 1 0 0 0 d0 page 8 40h com64 1 0 0 1 d0 page 9 43h icon(coms) 00 01 02 03 04 05 06 07 08 5d 5e 5f 60 61 62 63 64 65 0 d0 65 64 63 62 61 60 5f 5e 5d 08 07 06 05 04 03 02 01 00 1 d0 mx column address s0 s1 s2 s3 s4 s5 s6 s7 s8 s93 s94 s95 s96 s97 s98 s99 s100 s101 lcd out display data ram map (65 duty + icom)
ST7558 ver 2.3 24/56 2005/10/05 oscillator the on-chip oscillator provides the clock signal for the disp lay system. no external components are required and the osc input must be connected to vdd. an external clock signal, if used, is connected to this input. display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl (internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on-chip ram is generated in synchronization with the display clock and the display data latch circuit latches the 102-bit display data in synchronization with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m) which enables the lcd driver to make a ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. driving waveform and internal timing signal are shown in figure 13. fr(internal) m(internal) com0 com1 segn cl(internal) v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd 6465123456789101112 57585960616263646512345 fig.13 2-frame ac driving waveform (duty ratio: 1/65)
ST7558 ver 2.3 25/56 2005/10/05 lcd driver circuit 65-channel common drivers and 102-channel segment drivers conf igure this driver circuit. this lcd panel driver voltage depends on the combination of display data and m signal. seg 01234 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 v dd v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v ss v 1 v 2 v 3 v 4 v lcd -v 1 -v 2 -v 3 -v 4 -v lcd v ss v 4 v 3 v 2 v 1 v l2 -v 1 -v 2 -v 3 -v 4 -v lcd m com0 com1 com2 seg0 seg1 com0 to set0 com0 to set1 fig.15 typical lcd driver waveforms
ST7558 ver 2.3 26/56 2005/10/05 7. reset circuit setting resb to ? l ? or reset instruction can initialize internal function. when resb becomes ? l ? , following procedure is executed page address: 0 column address: 0 com scan direction my: 0 seg select direction mx: 0 oscillator: off power down mode (pd = 1) horizontal addressing (v = 0) normal instruction set (h = 0) display off (d = e = 0) address counter x [6:0] = 0, y [2:0] = 0 bias system (bs [2:0] = 0) vlcd is equal to 0; the hv generator is switched off (vop [6:0] = 0) after power-on, ram data are undefined while resb is ? l ? or reset instruction is executed, no instruction except read status can be accepted. reset status appears at db6. after db6 becomes ? l ? , any instruction can be accepted. resb must be connected to the reset pin of the mpu, and initialize the mpu and this lsi at the same time. the initialization by resb is essential before used.
ST7558 ver 2.3 27/56 2005/10/05 8. instruction table command byte instruction a0 wr (r/w) d7 d6 d5 d4 d3 d2 d1 d0 description h=0 or 1 nop 0 0 0 0 0 0 0 0 0 0 no operation reset 0 0 0 0 0 0 0 0 1 1 internal reset function set 0 0 0 0 1 0 0 pd v h power-down; entry mode; extended instruction control ext. display control 0 0 0 0 1 0 1 mx my 0 mirror x, mirror y read status byte 0 1 pd rst busy d e 1 0 1 read status byte read data 1 1 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 read data from ram write data 1 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 write data to ram command byte instruction a0 wr (r/w) d7 d6 d5 d4 d3 d2 d1 d0 description h=0 set v lcd range 0 0 0 0 0 1 0 0 0 prs v lcd range l/h select display control 0 0 0 0 0 0 1 d 0 e set display configuration set y address of ram 0 0 0 1 0 0 y 3 y 2 y 1 y 0 sets y address of ram 0 ?? y ??9 set x address of ram 0 0 1 x 6 x 5 x 4 x 3 x 2 x 1 x 0 sets x address of ram 0 ?? x ??101 loading control 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 loading control h=1 booster stages 0 0 0 0 0 0 1 0 pc 1 pc 0 booster voltage multiplication s/w internal register initial 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 s/w internal register initial bias system 0 0 0 0 0 1 0 bs 2 bs 1 bs 0 sets bias system (bsx) reserved 0 0 0 1 x x x x x x do not use set v op 0 0 1 v op6 v op5 v op4 v op3 v op2 v op1 v op0 write v op to register
ST7558 ver 2.3 28/56 2005/10/05 9. instruction description h=?0? or ?1? reset this instruction resets initial display line, column address, page address, and common output status select to their initial status. this instruction cannot initialize the lcd power supply, which is initialized by the resb pin. a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 1 1 !!!caution: this instruction cannot be used when using i 2 c interface function set a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 0 pd v h flag description pd all lcd outputs at vss (display off), bias generator and vlcd generator off, vlcd can be disconnected, oscillator off (external clock possible), ram contents not cleared; ram data can be written. pd=0:chip is active pd=1:chip is in power down mode v when v = 0, the horizontal addressing is selected. the data is written into the ddram as shown in fig13. when v = 1, the vertical addressing is selected. the data is written into the ddram as shown in fig12 h when h = 0 the commands ? display control ?| , ? set y address ?| and ? set x address ?| can be performed, when h = 1 the others can be executed. the commands ? write data ?| and ? function set ?| can be executed in both cases. h=0:use basic instruction set h=1:use extended instruction set ext. display control a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 1 mx my 0 flag description mx seg bi-direction selection mx=0:normal direction (seg0 ? seg101) mx=1:reverse direction (seg101 ? seg0) my com bi-direction selection see pad center coordinates at page 3~10 when using this register !!!caution:the common output pad should be care. the normal direction of common and reverse direction of common have different pad location, only one can be used. on the other hand, you must choose one kind, normal or reverse, and these two have different ito layout. moreover, using the normal layout, must set my=0; using the reverse layout ,must set my=1. ps. the normal and reverse pad location table are at page3 ~ page10
ST7558 ver 2.3 29/56 2005/10/05 read status byte indicates the internal status of the ST7558 a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 1 pd rst busy d e 1 0 1 flag description pd pd=0:chip is active pd=1:chip is in power down mode rst indicates the initialization is in progress by reset signal 0: chip is active,1:chip is being reset busy the device is busy when internal operation or reset. any instruction is rejected until busy goes low. 0:chip is active 1:chip is being busy d e the bits d and e select the display mode. 0 0 display blank 0 1 all display segments on 1 0 normal mode d,e 1 1 inverse video mode d2~d0 ST7558 will return the fix data ?101? as identification bit write data 8-bit data of display data from the microprocessor can be wr itten to the ram location specified by the column address and page address. the column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. during auto-increment, the column address wraps to 0 after the last column is written. a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 1 0 write data h=?0? set v lcd range v lcd range l/h select a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 0 0 0 prs prs=0:vlcd programming range low prs=1: vlcd programming range high display control this bits d and e selects the display mode. a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 d 0 e flag description d e the bits d and e select the display mode. 0 0 display off 1 0 normal display 0 1 all display segments on d,e 1 1 inverse video mode
ST7558 ver 2.3 30/56 2005/10/05 set y address of ram y [3:0] defines the y address vector address of the display ram. a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 0 y 3 y 2 y 1 y 0 x/y address range y 3 y 2 y 1 y 0 content allowed x-range 0 0 0 0 page0 (display ram) 0 to 101 0 0 0 1 page1 (display ram) 0 to 101 0 0 1 0 page2 (display ram) 0 to 101 0 0 1 1 page3 (display ram) 0 to 101 0 1 0 0 page4 (display ram) 0 to 101 0 1 0 1 page5 (display ram) 0 to 101 0 1 1 0 page6 (display ram) 0 to 101 0 1 1 1 page7 (display ram) 0 to 101 1 0 0 0 page8 (display ram) 0 to 101 1 0 0 1 page9 (display ram) 0 to 101 set x address of ram the x address points to the columns. the range of x is 0?101. a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x 6 x 5 x 4 x 3 x 2 x 1 x 0 column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 0 0 0 0 0 1 1 3 : : : : : : : : 1 1 0 0 0 1 0 98 1 1 0 0 0 1 1 99 1 1 0 0 1 0 0 100 1 1 0 0 1 0 1 101 set loading control improve out put driving in heavy loading a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 1
ST7558 ver 2.3 31/56 2005/10/05 h=?1? booster stages the ST7558 incorporates a software configurable voltage multipli er. after reset (resb), the default voltage multiplier is set to 2*vdd2. other voltage multiplier factors are set via the command ?set booster stages?. a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 0 pc 1 pc 0 flag description pc 1 pc 0 0 0 2*voltage multiplier 0 1 3*voltage multiplier 1 0 4*voltage multiplier pc 1 , pc0 1 1 5*voltage multiplier s/w initial internal register the 1 st instruction a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 1 1 0 the 2 nd instruction a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 0 0 1 0 system bias select lcd bias ratio of the voltage required for driving the lcd. a0 wr(r/w) d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 0 bs 2 bs 1 bs 0 bs 2 bs 1 bs 0 bias recommend duty 0 0 0 11 1:100 0 0 1 10 1:80 0 1 0 9 1:65/1:68 0 1 1 8 1:48 1 0 0 7 1/40:1/34 1 0 1 6 1/24 1 1 0 5 1:18/1:16 1 1 1 4 1:10/1:9/1:8 lcd bias voltage symbol bias voltage for 1/8 bias symbol bias voltage for 1/8 bias vlcdin vlcdin v3 2/8 x vlcdin v1 7/8 x vlcdin v4 1/8 x vlcdin v2 6/8 x vlcdin vss vss
ST7558 ver 2.3 32/56 2005/10/05 set vop value: the operation voltage v lcd can be set by software. v 0 =( a + v op ?? b ) (1) the parameters are explained in table 4.the maximum voltage that can be generated is depending on the vdd voltage and the display load current. two overlapping vlcd ranges are selectable via the command ? booster control ? . for the low (ps=0) range a=a1 and for the high (prs=1) range a=a2 with steps equal to ? b ? in both ranges. note that the charge pump is turned off if vop [6;0] and the bit prs are all set to zero. table 4 typical values for parameter for the hv-generator programming symbol value unit a1 2.94(prs=0) v a2 6.75(prs=1) v b 0.03 v caution as the programming range for the internally generated vlcdin allows values above the max allowed vlcdin, the customer has to ensure while setting the vop register that under all condition and including all tolerances the vlcd limit of max. 13v will never be exceeded. as vlcdin increases with lower temperatures, care must be taken not to set a vop generating a vlcdin voltage that will exceed the maximum of 10.6v when operating at ?v 40 j . 00 01 02 03 04 05 06 ..... 7e 7f 00 7d 01 02 03 04 05 06 ..... 7e 7d 7f c h a r g e p u m p o f f a 1 +b b a 2 v l2 low(prs=0) high(prs=1) vop [6:0](programmed) {00 hex? 7f hex} fig.19 v op programming of ST7558
ST7558 ver 2.3 33/56 2005/10/05 10. command description referential instruction setup flow: initializi ng with the built-in power supply circuits user system setup by external pins start of initialization power on(vdd-vss) keeping the /res pin="l" waiting for stabilizing the power release the reset state. (/resb pin="h") waiting reset circuit stablized(>1ms) end of initialization function set pd=0 ,v=0 , h=1 set bias system s/w internal register initial (2-byte) set booster 2x delay 50ms set vop hv_gen stages set booster 4x / 5x function set pd=0 , v=0 , h=0 set vlcd range(prs) display control d=1 e=0 (normal) set x , y address ext.display control fig.20 initializing with the built-in power supply circuits
ST7558 ver 2.3 34/56 2005/10/05 referential instruction setup flow: initializing without the built-in power supply circuits fig.21 initializing without built-in power supply circuits user system setup by external pins start of initialization power on(vdd-vss) keeping the /res pin="l" waiting for stabilizing the power release the reset state. (/resb pin="h") waiting reset circuit stablized(>1ms) waiting for stabilizing the lcd power levels end of initialization set power save function set pd=0 ,v=0 , h=1 set bias system s/w internal register initial function set pd=0 , v=0 , h=0 ext.display control display control d=1 e=0 (normal) set x , y address
ST7558 ver 2.3 35/56 2005/10/05 referential instruction setup flow: data displaying end of initialization display data ram addressing by instruction [set page address] [set column address] write display data by instruction [display data write] turn display on/off instruction [display on/off] end of data display fig.22 data displaying referential instruction setup flow: power off set power save by instruction power off(vdd-vss) optional status end of power off fig.23 power off
ST7558 ver 2.3 36/56 2005/10/05 11. limiting values in accordance with the absolute maximum rating system; see notes 1 and 2. parameter symbol conditions unit power supply voltage vdd ?0.5 ~ +5.0 v power supply voltage v0 3.0 ~ 12 v power supply voltage vlcdin ?0.3 ~ +13.5 v power supply voltage v1, v2, v3, v4 0.3 to vlcdin v input voltage vin ?0.5 to vdd+0.5 v output voltage vo ?0.5 to vdd+0.5 v operating temperature topr ?30 to +85 c storage temperature tstr ?65 to +150 c system (mpu) side ST7558 chip side v lcd v s s v 1 to v 4 v ss v dd v ss v dd notes 1. stresses above those listed under limiting values may cause permanent damage to the device. 2. parameters are valid over operating temperature range unl ess otherwise specified. all voltages are with respect to v ss unless otherwise noted. 3. insure that the voltage levels of v1, v2, v3, and v4 are always such that vout ? v0 ? v1 ? v2 ? v3 ? v4 ? vss
ST7558 ver 2.3 37/56 2005/10/05 12. dc characteristics v dd = 1.8 v to 3.3v; v ss = 0 v; v lcd = 3.0 to 13.0v; t amb = -30 j to +85 j ; unless otherwise specified . rating item symbol condition min. typ. max. units applicable pin operating voltage (1) vdd 1.8 ? 3.3 v vss*1 operating voltage (2) vdd2 (relative to vss) 1.8 ? 3.3 v vss2 high-level input voltage vihc 0.7 x vdd ? vdd v *2 low-level input voltage vilc vss ? 0.3 x vdd v *2 high-level output voltage vohc 0.7 x vdd ? vdd v *3 low-level output voltage volc vss ? 0.3 x vdd v *3 input leakage current ili vin = vdd or vss ?1.0 ? 1.0 g a *4 output leakage current ilo vin = vdd or vss ?3.0 ? 3.0 g a *5 vlcdin = 13.0 v ? 2.0 3.5 liquid crystal driver on resistance ron ta = 25c (relative to vss) vlcdin = 8.0 v ? 3.2 5.4 k [ segn comn *6 internal oscillator fosc ? 80 84 khz *7 external input fcl ? 80 84 khz osc oscillator frequency frame frequency fframe 1/65 duty ta = 25c ? 77 80.3 hz rating item symbol condition min. typ. max. units applicable pin input voltage vdd (relative to vss) 1.8 ? 3.3 v supply step-up output voltage circuit vlcdout (relative to vss) ? ? 13.5 v vlcdout internal power voltage regulator circuit operating voltage vlcdin (relative to vss) ? ? 13.5 v vlcdin
ST7558 ver 2.3 38/56 2005/10/05 bare dice consumption current : during display, with the internal power supply, current consumed by total ics when an external power supply(vdd,vdd2) is used . rating test pattern symbol condition min. typ. max. units notes display pattern snow iss vdd,vdd2 = 3.0 v, v0 ? vss = 9.0 v 4x booster 1/9 bias ? 300 400 g a *8 power down iss vdd=3.0v ta = 25c ? 0.01 2 g a notes to the dc characteristics 1. the maximum possible v lcd voltage that may be generated is dependent on voltage, temperature and (display) load. 2. internal clock 3. power-down mode. during power down all static currents are switched off. 4. if external v lcdin , the display load current is not transmitted to i dd . 5. v out external voltage applied to vlcdin pin; vlcdin disconnected from vlcdout (no connect) references for items market with * *1 while a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the mpu is being accessed. *2 the a0, d0 to d5, d6 (si), d7 (scl ), /rd (e), /wr ,/(r/w), csb, ims, osc, p/s, /dof, resb ,and mode terminals. *3 the d0 to d7, and osc terminals. *4 the a0,/rd (e), /wr ,/(r/w), csb, ims, osc, p/s, /dof, resb ,and mode terminals. *5 applies when the d0 to d5, d6 (si), d7 (scl) terminals are in a high impedance state. *6 these are the resistance values for when a 0.1 v voltage is applied between the output terminal segn or comn and the various power supply terminals (v1, v2, v3, and v4). these are specified for the operating voltage range. ron = 0.1 v / ? i (where ? i is the current that flows when 0.1 v is applied while the power supply is on.) *7 the relationship between the oscillator frequency and the frame rate frequency. *8,9it indicates the current consumed on ics alone when the internal oscillator circuit and display are turned on.
ST7558 ver 2.3 39/56 2005/10/05 13. timing characteristics system bus read/write characteristics 1 (for the 8080 series mpu) t ah8 t aw8 t cyc8 t cclr ,t cclw t cchr ,t cchw t ds8 t acc8 t oh8 t dh8 /cs wr,rd a0 d0 to d7 (write) d0 to d7 (read) fig 24. (vdd = 3.3v , ta =-30~85 x c) rating item signal symbol condition min. max. units address hold time tah8 10 ? address setup time taw8 0 ? system cycle time a0 tcyc8 240 ? enable l pulse width (write) tcclw 80 ? enable h pulse width (write) wr tcchw 80 ? enable l pulse width (read) tcclr 140 ? enable h pulse width (read) rd tcchr 80 write data setup time tds8 40 ? write address hold time tdh8 0 ? read access time tacc8 cl = 100 pf ? 70 read output disable time d0 to d7 toh8 cl = 100 pf 5 50 ns
ST7558 ver 2.3 40/56 2005/10/05 (vdd = 2.7 v , ta = -30~85c ) rating item signal symbol condition min. max. units address hold time tah8 15 ? address setup time taw8 0 ? system cycle time a0 tcyc8 400 ? enable l pulse width (write) tcclw 220 ? enable h pulse width (write) wr tcchw 180 ? enable l pulse width (read) tcclr 220 ? enable h pulse width (read) rd tcchr 180 ? write data setup time tds8 40 ? write address hold time tdh8 0 ? read access time tacc8 cl = 100 pf ? 140 read output disable time d0 to d7 toh8 cl = 100 pf 10 100 ns (vdd = 1.8v , ta = -30~85c ) rating item signal symbol condition min. max. units address hold time tah8 30 ? address setup time taw8 0 ? system cycle time a0 tcyc8 640 ? enable l pulse width (write) tcclw 360 ? enable h pulse width (write) wr tcchw 280 ? enable l pulse width (read) tcclr 360 ? enable h pulse width (read) rd tcchr 280 write data setup time tds8 80 ? write address hold time tdh8 30 ? read access time tacc8 cl = 100 pf ? 240 read output disable time d0 to d7 toh8 cl = 100 pf 10 200 ns *1 the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. when the system cycle time is extremely fas t, (tr +tf) ?? (tcyc8 ? tcclw ? tcchw) for (tr + tf) ?? (tcyc8 ? tcclr ? tcchr) are specified. *2 all timing is specified using 20% and 80% of vdd as the reference. *3 tcclw and tcclr are specified as the overlap between csb being ?l? and wr and rd being at the ?l? level.
ST7558 ver 2.3 41/56 2005/10/05 system bus read/write characteristics 1 (for the 6800 series mpu) t ah6 t aw6 t cyc6 t cclr ,t cclw t cchr ,t cchw t ds6 t acc6 t oh6 t dh6 cs1 (cs2="1") e a0 r/w d0 to d7 (write) d0 to d7 (read) fig 25. (v dd = 3.3 v , ta = -30~85c ) rating item signal symbol condition min. max. units address hold time tah6 10 ? address setup time taw6 0 ? system cycle time a0 tcyc6 240 ? enable l pulse width (write) tewlw 80 ? enable h pulse width (write) wr tewhw 80 ? enable l pulse width (read) tewlr 80 ? enable h pulse width (read) rd tewhr 140 write data setup time tds6 40 ? write address hold time tdh6 0 ? read access time tacc6 cl = 100 pf ? 70 read output disable time d0 to d7 toh6 cl = 100 pf 5 50 ns
ST7558 ver 2.3 42/56 2005/10/05 (vdd = 2.7v , ta =-30~85 x c ) rating item signal symbol condition min. max. units address hold time tah6 15 ? address setup time taw6 0 ? system cycle time a0 tcyc6 400 ? enable l pulse width (write) tewlw 220 ? enable h pulse width (write) wr tewhw 180 ? enable l pulse width (read) tewlr 220 ? enable h pulse width (read) rd tewhr 180 ? write data setup time tds6 40 ? write address hold time tdh6 0 ? read access time tacc6 cl = 100 pf ? 140 read output disable time d0 to d7 toh6 cl = 100 pf 10 100 ns (vdd =1.8v , ta =-30~85c ) rating item signal symbol condition min. max. units address hold time tah6 30 ? address setup time taw6 0 ? system cycle time a0 tcyc6 640 ? enable l pulse width (write) tewlw 360 ? enable h pulse width (write) wr tewhw 280 ? enable l pulse width (read) tewlr 360 ? enable h pulse width (read) rd tewhr 280 ? write data setup time tds6 80 ? write address hold time tdh6 30 ? read access time tacc6 cl = 100 pf ? 240 read output disable time d0 to d7 toh6 cl = 100 pf 10 200 ns *1 the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. when the system cycle time is extremely fas t, (tr +tf) ?? (tcyc6 ? tewlw ? tewhw) for (tr + tf) ?? (tcyc6 ? tewlr ? tewhr) are specified. *2 all timing is specified using 20% and 80% of vdd as the reference. *3 tewlw and tewlr are specified as the overlap between csb being ?l? and e.
ST7558 ver 2.3 43/56 2005/10/05 serial interface(4-line interface) t csh /cs1 (cs2="1") a0 si scl t ccss t sas t sah t scyc t slw t shw t sdh t sds t f t r fig 26. (v dd =3.3v,ta=-30~85 j ) rating item signal symbol condition min. max. units serial clock period tscyc 50 ? scl ?h? pulse width tshw 25 ? scl ?l? pulse width scl tslw 25 ? address setup time tsas 20 ? address hold time a0 tsah 10 ? data setup time tsds 20 ? data hold time si tsdh 10 ? cs-scl time tcss 20 ? cs-scl time csb tcsh 140 ? ns (v dd =2.7v,ta=-30~85 j ) rating item signal symbol condition min. max. units serial clock period tscyc 100 ? scl ?h? pulse width tshw 50 ? scl ?l? pulse width scl tslw 50 ? address setup time tsas 30 ? address hold time a0 tsah 20 ? data setup time tsds 30 ? data hold time si tsdh 20 ? cs-scl time tcss 30 ? cs-scl time csb tcsh 160 ? ns
ST7558 ver 2.3 44/56 2005/10/05 (v dd =1.8v,ta=-30~85 j ) rating item signal symbol condition min. max. units serial clock period tscyc 200 ? scl ?h? pulse width tshw 80 ? scl ?l? pulse width scl tslw 80 ? address setup time tsas 60 ? address hold time a0 tsah 30 ? data setup time tsds 60 ? data hold time si tsdh 30 ? cs-scl time tcss 40 ? cs-scl time csb tcsh 200 ? ns *1 the input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 all timing is specified using 20% and 80% of vdd as the standard. serial interface(i 2 c interface) sda scl t buf t dh;sta t low t hd;dat t high t su;dat (v dd = 1.8v~3.3v,ta=-30~85 j ) rating item signal symbol condition min. max. units scl clock frequency scl fsclk - 200 khz scl clock low period scl tlow 2.5 - us scl clock high period scl thigh 2.5 - us data set-up time si tsu;data 0.1 - us data hold time si thd;data 0 0.9 us scl,sda rise time scl tr 20+0.1cb 300 ns scl,sda fall time scl tf 20+0.1cb 300 ns capacitive load represented by each bus line cb - 400 pf setup time for a repeated start condition si tsu;sua 0.6 - us start condition hold time si thd;sta 0.6 - us setup time for stop ondition tsu;sto 0.6 - us tolerable spike width on bus tsw - 50 ns bus free time between a stop and start condition scl tbuf 2.5 us
ST7558 ver 2.3 45/56 2005/10/05 14. reset timing internal status t rw t r during reset reset complete /res fig 27. (vdd = 3.3v , ta = ?30 to 85c ) rating item signal symbol condition min. typ. max. units reset time tr ? ? 1 us reset ?l? pulse width resb trw 1 ? ? us (vdd = 2.7v , ta = ?30 to 85c ) rating item signal symbol condition min. typ. max. units reset time tr ? ? 1.5 us reset ?l? pulse width resb trw 1.5 ? ? us (vdd = 1.8v , ta = ?30 to 85c ) rating item signal symbol condition min. typ. max. units reset time tr ? ? 2.0 us reset ?l? pulse width resb trw 2.0 ? ? us
ST7558 ver 2.3 46/56 2005/10/05 15. application information table 5 programming example for ST7558 setp serial bus byte display operation 1 start csb is going low. 2 a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 0 function set. pd=0,v=0,select extended instruction set(h=0 mode) 3 a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 1 0 0 0 0 set v op v op is set to a+16*b[v] 4 a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 0 0 0 function set. pd=0,v=0,select normal instruction set(h=0 mode). 5 a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 0 0 display control. set normal mode(d=1,e=0) 6 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 1 1 0 data write. y,x are initialized to 0 by default, so they aren?t set here? 7 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 0 0 1 0 0 1 data write. 8 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 0 0 1 0 0 1 data write. 9 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 0 0 1 0 0 1 data write. 10 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 1 0 0 1 0 data write. 11 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 0 0 0 0 0 data write.
ST7558 ver 2.3 47/56 2005/10/05 12 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 0 0 0 0 0 1 data write. 13 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 1 1 1 1 1 1 data write. 14 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 0 0 0 0 0 1 data write. 15 a0 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 1 0 1 display control. set inverse video mode (d=1,e=1). 16 a0 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 0 0 0 set x address of ram. set address to ?0000000?. 17 a0 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 0 0 0 0 0 data write.
ST7558 ver 2.3 48/56 2005/10/05 programming example for ST7558(use i 2 c interface) setp serial bus byte display operation 1 i 2 c interface start 2 db7 db6 db5 db4 db3 db2 db1 db0 slave address for write 3 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 control byte with cleared co bit and a0 set to logic 0 4 db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 1 function set. pd=0,v=0,select extended instruction set(h=1 mode) 5 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 0 1 0 set bias system 6 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 0 0 0 set v op v op is set to a+16*b[v] 7 db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 0 0 0 function set. pd=0,v=0,select normal instruction set(h=0 mode). 8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 0 0 display control. set normal mode(d=1,e=0) 9 i 2 c interface start restart 10 db7 db6 db5 db4 db3 db2 db1 db0 slave address for write 11 db7 db6 db5 db4 db3 db2 db1 db0 1 1 0 0 0 0 0 0 control byte with set co bit and a0 set to logic 1 12 db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 0 0 1 1 0 data write. y,x are initialized to 0 by default, so they aren?t set here? 13 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 1 0 0 1 data write. 14 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 1 0 0 1 data write.
ST7558 ver 2.3 49/56 2005/10/05 15 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 1 0 0 1 data write. 16 db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 1 0 0 1 0 data write. 17 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 data write. 18 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 0 1 data write. 19 db7 db6 db5 db4 db3 db2 db1 db0 0 1 1 1 1 1 1 1 data write. 20 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 0 1 data write. 21 i 2 c interface start restart 22 db7 db6 db5 db4 db3 db2 db1 db0 slave address for write 23 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 0 0 0 0 control byte with cleared co bit and a0 set to logic 1 24 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 1 0 1 display control. set inverse video mode (d=1,e=1). 25 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 0 0 0 0 control byte with cleared co bit and a0 set to logic 1
ST7558 ver 2.3 50/56 2005/10/05 26 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 0 0 0 0 set x address of ram. set address to ?0000000?. 27 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 0 0 control byte with set co bit and a0 set to logic 0 28 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data write. 29 i 2 c interface start restart 30 db7 db6 db5 db4 db3 db2 db1 db0 slave address for write 31 db7 db6 db5 db4 db3 db2 db1 db0 1 1 0 0 0 0 0 0 control byte with set co bit and a0 set to logic 1 32 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 0 0 0 0 set x address of ram. set address to ?0000000?. 33 db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 0 0 0 0 control byte with cleared co bit and a0 set to logic 0
ST7558 ver 2.3 51/56 2005/10/05 the pinning of the ST7558 is optimized for single plane wiring e.g. for chip-on-glass display modules. display size: 65x102 pixels. display 102x 65 pixels ST7558 32 102 33 8 v dd v ss c vdd c lvcd v dd2 v dd v ss1 v ss2 v lcdout v lcdin i/o fig 28. application diagram: internal charge pump is used and single v dd v dd2 c vdd2 display 102 x 65 pixels ST7558 32 102 33 8 v ss c lvcd v dd2 v dd v ss1 v ss2 v lcdout v lcdin i/o v dd c vdd fig 29. application diagram: internal charge pump is used and two separate vdd(v dd2 )
ST7558 ver 2.3 52/56 2005/10/05 the required minimum value for the external capacitors in an application with the ST7558 are: c vlcd = min. 100nf c vdd,2 = min. 1.0 g f higher capacitor values are recommended for ripple reduction. display 102 x 65 pixels ST7558 32 102 33 8 v dd2 v ss c vdd v dd2 v dd v ss1 v ss2 v lcdout v lcdin i/o v l2 fig 30. application diagram : external high voltage generation is used
ST7558 ver 2.3 53/56 2005/10/05 16.the mpu interface (reference examples) the ST7558 series can be connected to either 80x86 series mpus or to 6800 series mpus. moreover, using the serial interface it is possible to operate the ST7558 series chips with fewer signal lines. the display area can be enlarged by using multiple ST7558 series chips. when this is done, the chip select signal can be used to select the individual ics to access. (1) 8080 series mpus a0 a1 to a7 iorq do to d7 rd wr res v cc gnd mpu a0 /cs d0 to d7 e (/rd) r/w (/wr) /res v dd v ss ST7558 decoder reset ims ps v dd v ss (2) 6800 series mpus a0 a1 to a7 iorq do to d7 rd wr res v cc gnd mpu a0 d0 to d7 /rd (e) /wr (r/w) /res v dd v ss ST7558 /cs decoder reset ims ps v dd v ss (3) using the serial interface (4-line interface) a0 a1 to a7 port 1 port 2 res v cc gnd a0 /cs si scl /res v dd v ss decoder reset ims ps v dd v ss mpu ST7558
ST7558 ver 2.3 54/56 2005/10/05 (4) using the serial interface (i 2 c interface) port 1 port 2 res v cc gnd sda scl /res v dd v ss reset ims ps v dd v ss mpu ST7558
ST7558 ver 2.3 55/56 2005/10/05 65-duty/serial-4line/vlcdin-internal/vdd2=vdd/internal-osc c o m 5 2 c o m 5 3 c o m 4 3 c o m 4 4 c o m 1 0 c o m 1 1 c o m 1 9 c o m 2 0 ?k?k?k ?k?k?k c 65-duty/serial-i2c/vlcdin-internal/vdd2=vdd/internal-osc
ST7558 ver 2.3 56/56 2005/10/05 ST7558 v l c d o u t v l c d i n v s s v s s 2 v 4 v 3 v 2 v 1 v 0 o s c v d d t 1 0 t 1 1 p s v d d i m s c s a 0 r w r e r d v r s t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 v d d d 1 d 0 d 3 d 2 d 4 d 6 d 5 v d d 2 d 7 v d d 2 v d d v d d t 9 r e s e r v e c o m 3 1 c o m 2 1 c o m 2 2 v s s 2 v s s c o m s 2 r e s c o m 5 4 c o m 5 5 c o m 6 4 c o m 5 2 c o m 5 3 c o m 4 3 c o m 4 4 c o m 1 0 c o m 1 1 c o m 1 9 c o m 2 0 c o m 9 c o m 8 c o m 4 2 c o m 4 1 c o m 2 c o m 1 c o m 0 c o m s 1 s e g 1 0 1 s e g 1 0 0 s e g 1 s e g 0 r e s e r v e c o m 3 2 c o m 3 3 c o m 3 4 ?k ?k ?k?k?k ?k?k?k ?k?k?k ?k?k?k ?k?k ?k?k?k ?k?k?k ?k?k?k ?k?k ?k?k v s s v d d s c l s d a r e s os c - - vd d ( inter na l) t10 -- v ss (default) t11 -- vdd ps -- vss ims -- vss ( i2c ) cs - - vdd (no used ) a0 - - vd d (no us ed ) rwr -- vdd (no used) er d - - vd d ( n o u se d) d0 ~ d 1 -- vs s (a ddr es s) d2 ~ d6 -- sda (n eed exter nal pull u p r esister) d7 - - scl (need external pull up resister) ito pad for monitor v0 te st rr vd d vdd v o u c t ( serial )

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